Performance Evolution of Multi-Valued Nano Inverters

Document Type : Original Article

Authors

1 University of Science and Culture

2 University of Science and Culture, Bahar st, Shahid Qamushi st, Ashrafi Esfahani Bulvar

Abstract

In this paper, recent improvements of multi-valued inverters with focus on their superiority over conventional binary logic systems is investigated. The most concentration is on cutting edge transistors in order to utilize logic gates, with a focus on Carbon Nanotube Field Effect Transistors (CNTFET), and Graphene Nanoribbon Field Effect Transistors (GNRFET). The structural and operational principle of these emerging transistors are analyzed according to the comparative evaluation of their performance in terms of variety of parameters such as PDP, delay, power consumption and fabrication complexity. In this paper, the special attention is on CNTFET and GNRFET-based ternary and quaternary inverters. However, in order to have a better approach on performance of multi-valued inverters and the best candidate, pentarnary and binary inverters are investigated. The findings shows that the GNRFET-based inverters have lower propagation delay and less power consumption in comparison with CNTFET counterparts, despite certain trade-offs associated with increased power consumption in specific GNRFET implementations.

Keywords

References

[1]   S. Lin, Y.-B. Kim, and F. Lombardi, "CNTFET-based design of ternary logic gates and arithmetic circuits," IEEE transactions on nanotechnology, vol. 10, no. 2, pp. 217-225, 2009.
[2]   M. H. Moaiyeri, K. Navi, and O. Hashemipour, "Design and evaluation of CNFET-based quaternary circuits," Circuits, Systems, and Signal Processing, vol. 31, no. 5, pp. 1631-1652, 2012.
[3]   H. Lee, S. Kim, J. Kim, J. Jeong, J. Yang, and T. Song, "Ternary Toward Binary: Circuit-Level Implementation of Ternary Logic Using Depletion-Mode and Conventional MOSFETs," IEEE Access, 2024.
[4]   S. Tabrizchi, F. Sharifi, A.-H. Badawy, and Z. Saifullah, "Enabling energy-efficient ternary logic gates using CNFETs," in 2017 IEEE 17th International Conference on Nanotechnology (IEEE-NANO), 2017: IEEE, pp. 542-547.
[5]   G. E. Moore, "Cramming more components onto integrated circuits," ed: McGraw-Hill New York, 1965.
[6]   K. C. Smith, "A multiple valued logic: a tutorial and appreciation," Computer, vol. 21, no. 4, pp. 17-27, 2002.
[7]   Hurst, "Multiple-valued logic—Its status and its future," IEEE Transactions on computers, vol. 100, no. 12, pp. 1160-1179, 1984.
[8]   F. Sharifi, M. H. Moaiyeri, K. Navi, and N. Bagherzadeh, "Quaternary full adder cells based on carbon nanotube FETs," Journal of Computational Electronics, vol. 14, no. 3, pp. 762-772, 2015.
[9]   E. Dubrova, "Multiple-valued logic in VLSI: challenges and opportunities," in Proceedings of NORCHIP, 1999, vol. 99, no. 1999, pp. 340-350.
[10] A. Raychowdhury and K. Roy, "Carbon-nanotube-based voltage-mode multiple-valued logic design," IEEE Transactions on Nanotechnology, vol. 4, no. 2, pp. 168-179, 2005.
[11] F. Zahoor et al., "Design implementations of ternary logic systems: A critical review," Results in Engineering, vol. 23, p. 102761, 2024.
[12] Y. Yasuda, Y. Tokuda, S. Zaima, K. Pak, T. Nakamura, and A. Yoshida, "Realization of quaternary logic circuits by n-channel MOS devices," IEEE Journal of Solid-State Circuits, vol. 21, no. 1, pp. 162-168, 1986.
[13] M. H. Moaiyeri, R. F. Mirzaee, A. Doostaregan, K. Navi, and O. Hashemipour, "A universal method for designing low‐power carbon nanotube FET‐based multiple‐valued logic circuits," IET Computers & Digital Techniques, vol. 7, no. 4, pp. 167-181, 2013.
[14] T. Araki, H. Tatsumi, M. Mukaidono, and F. Yamamoto, "Minimization of incompletely specified regular ternary logic functions and its application to fuzzy switching functions," in Proceedings. 1998 28th IEEE International Symposium on Multiple-Valued Logic (Cat. No. 98CB36138), 1998: IEEE, pp. 289-296.
[15] J. T. Butler and H. G. Kerkhoff, "Multiple-valued CCD circuits," Computer, vol. 21, no. 4, pp. 58-69, 2002.
[16] S. Onneweer, H. Kerkhoff, and J. Butler, "Structural computer-aided design of current-mode CMOS logic circuits," 1988.
[17] F. Pelayo, A. Prieto, A. Lloris, and J. Ortega, "CMOS current-mode multivalued PLAs," IEEE transactions on circuits and systems, vol. 38, no. 4, pp. 434-441, 2002.
[18] M. Heydari, A. Rezai, and F. Javaheri, "Design of Novel 2: 4 Decoder Circuits for Quantum-dot Cellular Automata Technology," Modeling and Simulation in Electrical and Electronics Engineering, vol. 3, no. 4, pp. 23-30, 2024.
[19] M. Balali, A. Rezai, H. Balali, F. Rabiei, and S. Emadi, "Towards coplanar quantum-dot cellular automata adders based on efficient three-input XOR gate," Results in physics, vol. 7, pp. 1389-1395, 2017.
[20] A. Karimi and A. Rezai, "High‐performance digital logic implementation approach using novel Memristor‐based multiplexer," International Journal of Circuit Theory and Applications, vol. 47, no. 12, pp. 1933-1947, 2019.
[21] A. Amirany, K. Jafari, and M. H. Moaiyeri, "BVA-NQSL: A bio-inspired variation-aware nonvolatile quaternary spintronic latch," IEEE Magnetics Letters, vol. 11, pp. 1-5, 2020.
[22] M. BahmanAbadi, A. Amirany, M. H. Moaiyeri, and K. Jafari, "Towards nonvolatile spintronic quaternary flip-flop and register design," in Spin, 2023, vol. 13, no. 03: World Scientific, p. 2350015.
[23] S. Nabi and A. Rezai, "Performance analysis of FET-based Universal gates in multi-valued logic," Computational Sciences and Engineering, 2025.
[24] A. Karimi and A. Rezai, "A design methodology to optimize the device performance in CNTFET," ECS Journal of Solid State Science and Technology, vol. 6, no. 8, p. M97, 2017.
[25] M. Shafizadeh and A. Rezai, "Improved device performance in a CNTFET using La 2 O 3 high-κ dielectrics," Journal of Computational Electronics, vol. 16, no. 2, pp. 221-227, 2017.
[26] B. D. Madhuri and S. Sunithamani, "Design of ternary logic gates and circuits using GNRFETs," IET Circuits, Devices & Systems, vol. 14, no. 7, pp. 972-979, 2020.
[27] P. Gowrisankar, "Design of multi-valued ternary logic gates based on emerging sub-32nm technology," in 2017 Third International Conference on Science Technology Engineering & Management (ICONSTEM), 2017: IEEE, pp. 1023-1031.
[28] S. Karmakar, J. A. Chandy, and F. C. Jain, "Design of ternary logic combinational circuits based on quantum dot gate FETs," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, no. 5, pp. 793-806, 2012.
[29] S. S. Dan and S. Mahapatra, "Impact of energy quantisation in single electron transistor island on hybrid complementary metal oxide semiconductor–single electron transistor integrated circuits," IET circuits, devices & systems, vol. 4, no. 5, pp. 449-457, 2010.
[30] J. Appenzeller, "Carbon nanotubes for high-performance electronics—Progress and prospect," Proceedings of the IEEE, vol. 96, no. 2, pp. 201-211, 2008.
[31] A. Hazeghi, T. Krishnamohan, and H.-S. P. Wong, "Schottky-barrier carbon nanotube field-effect transistor modeling," IEEE Transactions on Electron Devices, vol. 54, no. 3, pp. 439-445, 2007.
[32] A. Naderi and M. Ghodrati, "An efficient structure for T-CNTFETs with intrinsic-n-doped impurity distribution pattern in drain region," Turkish Journal of Electrical Engineering and Computer Sciences, vol. 26, no. 5, pp. 2335-2346, 2018.
[33] V. Prasad and D. Das, "A review on MOSFET-Like CNTFETs," Sci. Technol. J, vol. 4, no. 2, pp. 124-129, 2016.
[34] S. J. Basha and P. Venkatramana, "High performance quaternary logic designs using GNFETs," e-Prime-Advances in Electrical Engineering, Electronics and Energy, vol. 5, p. 100197, 2023.
[35] M. Nayeri, P. Keshavarzian, and M. Nayeri, "Approach for MVL design based on armchair graphene nanoribbon field effect transistor and arithmetic circuits design," Microelectronics Journal, vol. 92, p. 104599, 2019.
[36] X. Wang and H. Dai, "Etching and narrowing of graphene from the edges," Nature chemistry, vol. 2, no. 8, pp. 661-665, 2010.
[37] M. Khandelwal and N. Sharan, "Design and performance comparison of CNTFET-based binary and ternary logic inverter and decoder with 32 nm CMOS technology," in Advances in Computer and Computational Sciences: Proceedings of ICCCCS 2016, Volume 1: Springer, 2017, pp. 429-437.
[38] G. Singh, M. Kaur, and Y. Kumar, "CNTFET for Logic Gates Design," in Major Applications of Carbon Nanotube Field-Effect Transistors (CNTFET): IGI Global Scientific Publishing, 2020, pp. 54-71.
[39] E. Abbasian, S. Sofimowloodi, and A. Sachdeva, "Highly-efficient CNTFET-based unbalanced ternary logic gates," ECS Journal of Solid State Science and Technology, vol. 12, no. 3, p. 031007, 2023.
[40] M. H. Moaiyeri, A. Doostaregan, and K. Navi, "Design of energy-efficient and robust ternary circuits for nanotechnology," IET Circuits, Devices & Systems, vol. 5, no. 4, pp. 285-296, 2011.
[41] H. Samadi, A. Shahhoseini, and F. Aghaei-liavali, "A new method on designing and simulating CNTFET_based ternary gates and arithmetic circuits," Microelectronics Journal, vol. 63, pp. 41-48, 2017.
[42] K. J. Krishna, S. R. Kumar, J. S. P. Dharshini, B. Himabindu, B. Dinesh, and B. Krupakar, "Design of Ternary Logic gates and Arithmetic Circuits to Enhance Energy Efficiency using CNTFET Technology," in International Conference on Computer Science and Communication Engineering (ICCSCE 2025), 2025: Atlantis Press, pp. 2279-2294.
[43] S. RatanKumar, L. K. Rao, and M. K. Kumar, "Design of ternary full-adder and full-subtractor using pseudo NCNTFETs," e-Prime-Advances in Electrical Engineering, Electronics and Energy, vol. 6, p. 100285, 2023.
[44] S. A. Ebrahimi, M. R. Reshadinezhad, A. Bohlooli, and M. Shahsavari, "Efficient CNTFET-based design of quaternary logic gates and arithmetic circuits," Microelectronics Journal, vol. 53, pp. 156-166, 2016.
[45] Z. T. Sandhie, F. U. Ahmed, and M. H. Chowdhury, "Design of ternary logic and arithmetic circuits using GNRFET," IEEE Open Journal of Nanotechnology, vol. 1, pp. 77-87, 2020.
[46] K. Mahesh and S. Shameem, "High-speed and power-efficient ternary logic designs using GNR transistors," e-Prime-Advances in Electrical Engineering, Electronics and Energy, vol. 7, p. 100439, 2024.
[47] M. K. Majumder, N. R. Kukkam, and B. K. Kaushik, "Frequency response and bandwidth analysis of multi‐layer graphene nanoribbon and multi‐walled carbon nanotube interconnects," Micro & Nano Letters, vol. 9, no. 9, pp. 557-560, 2014.
[48] G. S. Simate, S. E. Iyuke, S. Ndlovu, C. S. Yah, and L. F. Walubita, "The production of carbon nanotubes from carbon dioxide: challenges and opportunities," Journal of Natural Gas Chemistry, vol. 19, no. 5, pp. 453-460, 2010.
[49] J. Banothu, "Design of High-Speed GNRFET Based Ternary Logic Circuits," International Journal of Applied Mathematics, vol. 38, no. 9s, pp. 913-935, 2025.
[50] Z. T. Sandhie, F. U. Ahmed, and M. Chowdhury, "GNRFET based ternary logic–prospects and potential implementation," in 2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS), 2020: IEEE, pp. 1-4.
[51] D. G. Anil, Y. Bai, and Y. Choi, "Performance evaluation of ternary computation in SRAM design using graphene nanoribbon field effect transistors," in 2018 IEEE 8th Annual Computing and Communication Workshop and Conference (CCWC), 2018: IEEE, pp. 382-388.
Contributions of Science and Technology for Engineering
Volume 3, Issue 3
August 2026
Pages 11-25

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History

  • Receive Date: 26 December 2025
  • Revise Date: 27 April 2026
  • Accept Date: 26 August 2026
  • First Publish Date: 31 August 2026
  • Publish Date: 31 August 2026

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