The threshold voltage of a MOSFET, represented by VTH, is a major parameter in the circuit design, and the lack of an accurate equation for the threshold voltage of transistors is one of the main challenges for integrated circuit designers. Based on the data obtained from the simulation, the present paper aims to investigate the effect of bias voltages (VGS, VDS, and VBS), transistor's dimensions (W and L), and temperature (T) on the value of threshold voltage, followed by the use of Levenberg-Marquardt method to propose a new equation for obtaining the threshold voltage value regarding different parameters. The obtained equation can be helpful for the design and manual calculations of the integrated circuits. Furthermore, various simulations were performed to evaluate the validity and accuracy of the obtained equation, indicating excellent consistency between the proposed equation and simulation results
Yu, X., Cheng, R., Liu, W., Qu, Y., Han, J., Chen, B., Lu, J., & Zhao, Y. (2018). A Fast Vth Measurement (FVM) Technique for NBTI Behavior Characterization. IEEE Electron Device Letters, 39(2), 172–175. doi:10.1109/LED.2017.2781243.
Luo, T. C., Chao, M. C. T., Tseng, H. C., Goto, M., Fisher, P. A., Chang, Y. Y., Chang, C. M., Takao, T., Iwasaki, K., & Lee, C. M. (2014). Fast transistor threshold voltage measurement method for high-speed, high-accuracy advanced process characterization. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22(5), 1138–1149. doi:10.1109/TVLSI.2013.2265299.
Siebel, O. F., Schneider, M. C., & Galup-Montoro, C. (2012). MOSFET threshold voltage: Definition, extraction, and some applications. Microelectronics Journal, 43(5), 329–336. doi:10.1016/j.mejo.2012.01.004.
Flandre, D., Kilchytska, V., & Rudenko, T. (2010). GmId method for threshold voltage extraction applicable in advanced MOSFETs with nonlinear behavior above threshold. IEEE Electron Device Letters, 31(9), 930–932. doi:10.1109/LED.2010.2055829.
Agarwal, H., Gupta, C., Kushwaha, P., Yadav, C., Duarte, J. P., Khandelwal, S., Hu, C., & Chauhan, Y. S. (2015). Analytical modeling and experimental validation of threshold voltage in BSIM6 MOSFET model. IEEE Journal of the Electron Devices Society, 3(3), 240–243. doi:10.1109/JEDS.2015.2415584.
de Jesus Costa, A., Alves, B. J., de Santana Soares, S., Santana, E. P., & Cunha, A. I. A. (2017). Improving a MOSFET model for design by hand. 2017 IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS). doi:10.1109/lascas.2017.7948079.
Chanda, M., Jain, S., De, S., & Sarkar, C. K. (2015). Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23(12), 2782–2790. doi:10.1109/TVLSI.2014.2385817.
Zhang, Y., & Yuan, J. S. (2012). CMOS transistor amplifier temperature compensation: Modeling and analysis. IEEE Transactions on Device and Materials Reliability, 12(2), 376–381. doi:10.1109/TDMR.2011.2180388.
De Oliveira, A. C., Cordova, D., Klimach, H., & Bampi, S. (2017). Picowatt, 0.45-0.6 v Self-Biased Subthreshold CMOS Voltage Reference. IEEE Transactions on Circuits and Systems I: Regular Papers, 64(12), 3036–3046. doi:10.1109/TCSI.2017.2754644.
Luong, P., Christoffersen, C., Rossi-Aicardi, C., & Dualibe, C. (2017). Nanopower, Sub-1 V, CMOS Voltage References with Digitally-Trimmable Temperature Coefficients. IEEE Transactions on Circuits and Systems I: Regular Papers, 64(4), 787–798. doi:10.1109/TCSI.2016.2632072.
Gupta, M., & Kranti, A. (2017). Variation of Threshold Voltage with Temperature in Impact Ionization-Induced Steep Switching Si and Ge Junctionless MOSFETs. IEEE Transactions on Electron Devices, 64(5), 2061–2066. doi:10.1109/TED.2017.2679218.
Fasarakis, N., Karatsori, T., Tassis, D. H., Theodorou, C. G., Andrieu, F., Faynot, O., Ghibaudo, G., & Dimitriadis, C. A. (2014). Analytical modeling of threshold voltage and interface ideality factor of nanoscale ultrathin body and buried oxide SOI MOSFETs with back gate control. IEEE Transactions on Electron Devices, 61(4), 969–975. doi:10.1109/TED.2014.2306015.
Mezzomo, C. M., Bajolet, A., Cathignol, A., Di Frenza, R., & Ghibaudo, G. (2011). Characterization and modeling of transistor variability in advanced CMOS technologies. IEEE Transactions on Electron Devices, 58(8), 2235–2248. doi:10.1109/TED.2011.2141140.
Johns, D. A., & Martin, K. (2008). Analog integrated circuit design. John Wiley & Sons, Hoboken, United States.
Yu, X., Cheng, R., Liu, W., Qu, Y., Han, J., Chen, B., Lu, J., & Zhao, Y. (2018). A Fast Vth Measurement (FVM) Technique for NBTI Behavior Characterization. IEEE Electron Device Letters, 39(2), 172–175. doi:10.1109/LED.2017.2781243.
Luo, T. C., Chao, M. C. T., Tseng, H. C., Goto, M., Fisher, P. A., Chang, Y. Y., Chang, C. M., Takao, T., Iwasaki, K., & Lee, C. M. (2014). Fast transistor threshold voltage measurement method for high-speed, high-accuracy advanced process characterization. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22(5), 1138–1149. doi:10.1109/TVLSI.2013.2265299.
Siebel, O. F., Schneider, M. C., & Galup-Montoro, C. (2012). MOSFET threshold voltage: Definition, extraction, and some applications. Microelectronics Journal, 43(5), 329–336. doi:10.1016/j.mejo.2012.01.004.
Flandre, D., Kilchytska, V., & Rudenko, T. (2010). GmId method for threshold voltage extraction applicable in advanced MOSFETs with nonlinear behavior above threshold. IEEE Electron Device Letters, 31(9), 930–932. doi:10.1109/LED.2010.2055829.
Agarwal, H., Gupta, C., Kushwaha, P., Yadav, C., Duarte, J. P., Khandelwal, S., Hu, C., & Chauhan, Y. S. (2015). Analytical modeling and experimental validation of threshold voltage in BSIM6 MOSFET model. IEEE Journal of the Electron Devices Society, 3(3), 240–243. doi:10.1109/JEDS.2015.2415584.
de Jesus Costa, A., Alves, B. J., de Santana Soares, S., Santana, E. P., & Cunha, A. I. A. (2017). Improving a MOSFET model for design by hand. 2017 IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS). doi:10.1109/lascas.2017.7948079.
Chanda, M., Jain, S., De, S., & Sarkar, C. K. (2015). Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23(12), 2782–2790. doi:10.1109/TVLSI.2014.2385817.
Zhang, Y., & Yuan, J. S. (2012). CMOS transistor amplifier temperature compensation: Modeling and analysis. IEEE Transactions on Device and Materials Reliability, 12(2), 376–381. doi:10.1109/TDMR.2011.2180388.
De Oliveira, A. C., Cordova, D., Klimach, H., & Bampi, S. (2017). Picowatt, 0.45-0.6 v Self-Biased Subthreshold CMOS Voltage Reference. IEEE Transactions on Circuits and Systems I: Regular Papers, 64(12), 3036–3046. doi:10.1109/TCSI.2017.2754644.
Luong, P., Christoffersen, C., Rossi-Aicardi, C., & Dualibe, C. (2017). Nanopower, Sub-1 V, CMOS Voltage References with Digitally-Trimmable Temperature Coefficients. IEEE Transactions on Circuits and Systems I: Regular Papers, 64(4), 787–798. doi:10.1109/TCSI.2016.2632072.
Gupta, M., & Kranti, A. (2017). Variation of Threshold Voltage with Temperature in Impact Ionization-Induced Steep Switching Si and Ge Junctionless MOSFETs. IEEE Transactions on Electron Devices, 64(5), 2061–2066. doi:10.1109/TED.2017.2679218.
Fasarakis, N., Karatsori, T., Tassis, D. H., Theodorou, C. G., Andrieu, F., Faynot, O., Ghibaudo, G., & Dimitriadis, C. A. (2014). Analytical modeling of threshold voltage and interface ideality factor of nanoscale ultrathin body and buried oxide SOI MOSFETs with back gate control. IEEE Transactions on Electron Devices, 61(4), 969–975. doi:10.1109/TED.2014.2306015.
Mezzomo, C. M., Bajolet, A., Cathignol, A., Di Frenza, R., & Ghibaudo, G. (2011). Characterization and modeling of transistor variability in advanced CMOS technologies. IEEE Transactions on Electron Devices, 58(8), 2235–2248. doi:10.1109/TED.2011.2141140.
Johns, D. A., & Martin, K. (2008). Analog integrated circuit design. John Wiley & Sons, Hoboken, United States.
Ebrahimi, A. , & Adarang, H. (2024). Modeling MOSFET Threshold Voltage in TSMC 0.18um CMOS for Integrated Circuits Design. Contributions of Science and Technology for Engineering, 1(1), 1-11. doi: 10.22080/cste.2024.5008
MLA
Amir Ebrahimi; Habib Adarang. "Modeling MOSFET Threshold Voltage in TSMC 0.18um CMOS for Integrated Circuits Design", Contributions of Science and Technology for Engineering, 1, 1, 2024, 1-11. doi: 10.22080/cste.2024.5008
HARVARD
Ebrahimi, A., Adarang, H. (2024). 'Modeling MOSFET Threshold Voltage in TSMC 0.18um CMOS for Integrated Circuits Design', Contributions of Science and Technology for Engineering, 1(1), pp. 1-11. doi: 10.22080/cste.2024.5008
CHICAGO
A. Ebrahimi and H. Adarang, "Modeling MOSFET Threshold Voltage in TSMC 0.18um CMOS for Integrated Circuits Design," Contributions of Science and Technology for Engineering, 1 1 (2024): 1-11, doi: 10.22080/cste.2024.5008
VANCOUVER
Ebrahimi, A., Adarang, H. Modeling MOSFET Threshold Voltage in TSMC 0.18um CMOS for Integrated Circuits Design. Contributions of Science and Technology for Engineering, 2024; 1(1): 1-11. doi: 10.22080/cste.2024.5008